Timing
This page provides timing specifications and describes each specification in detail.
| TIMING SPECIFICATIONS | |||
| SUBSYSTEM | Specification | Typical Value | Type |
| IMU | Motion to Message Latency | latency | |
| IMU | Timestamp Repeatability | error | |
| GPIO | GPIO Timestamp Accuracy | error | |
Explanation of Specifications
Motion to Message Latency
This specification describes the amount of time (latency) it takes from the moment a motion (either an acceleration or a rotation) is imparted to the 3DM-CV7 to when a message is generated that captures the magnitude of that motion.
This specification does not include the time it then takes to send the message over the communications interface.
Timestamp Repeatability
This specification accounts for variations in timestamp accuracy introduced by internal hardware processing delays. Repeatability will also be impacted by any additional clock jitter introduced by an external clock.
See PPS and Synchronizing Data Output with an External System for options the 3DM-CV7 provides for applying an external clock.
GPIO Timestamp Accuracy
The accuracy of the timestamp generated from a GPIO Event Trigger with the pin set to the hardware timestamping feature.
Additional Sources of Latency
- Transmitting data can take a significant amount of time. The device is not blocked from processing during transmission time, but it does factor into the latency between the originating event and the final application. If the UART is used, the baud rate will determine how long it takes to transfer a given packet. Therefore, it is recommended to use the highest possible baud rate if latency is a concern. USB offers much higher transfer speeds, but it comes at the expense of non-deterministic delays and stalls imparted by the host, which can be significant.
- Latency specifications can be subject to device configuration. Enabling more features or MIP messages can increase processing time and latency.
- These specifications are not valid when a timing overrun condition exists (i.e. if the timing overrun bit is set in the Built-in Tests result). This can occur if too many features are enabled simultaneously and must be avoided for proper operation.